In the field of integrated circuits and semiconductor devices, it is known that electronic circuits located on a semiconductor substrate are vulnerable to the injection of charge carriers into the semiconductor substrate. In particular, the injection of charge carriers into the semiconductor substrate can seriously disturb the operation of the electronic circuitry located thereon, and in more severe cases can cause a well known phenomenon known as latch-up.
A known cause of this unwanted injection of charge carriers into the semiconductor substrate is high negative stress current or negative voltage occurring on external pins of a semiconductor device, thereby activating parasitic effects of p-n junctions within the substrate. For example, it is known for semiconductor devices to comprise power MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) that are used to drive external devices such as lights, motors, etc. Often, such external devices comprise inductive properties whereby, when the MOSFET is turned ‘off’, the external devices initially continue to draw current. As a result, the MOSFET terminal coupled to the external devices will experience a high negative stress current. Due to the structure of a MOSFET terminal, when such a negative current is applied to the terminal of the MOSFET, a p-n junction of the MOSFET creates a parasitic diode structure, which injects unwanted charge carriers into the substrate of the semiconductor device.
FIG. 1 illustrates an example of a typical structure for an N-channel MOSFET 100 located on a semiconductor substrate 110. The semiconductor substrate 110 comprises semiconductor material doped with positive charge carriers, and provides a p-doped ‘body’ for the N-channel MOSFET 100. Two n-doped regions 120, 130, doped with negative charge carriers, are formed within the surface of the semiconductor substrate 110, each of which is operably coupled to a conductive contact 140, 150, one for each of a source and drain terminal of the N-channel MOSFET 100 respectively. A third conductive contact 160, providing a gate terminal for the N-channel MOSFET 100, is located generally between the two n-doped regions 120, 130, adjacent a region of the p-doped semiconductor substrate 110. An insulating layer 170 is located between the gate contact 160 and the p-doped semiconductor substrate 110. When a positive voltage is applied to the gate contact 160, positive charge carriers build up within the gate contact 160, repelling the positive charge carriers within the p-doped substrate 110 away from the gate contact 160. If a sufficiently high voltage is applied to the gate contact 160, a depletion layer is formed within the p-doped substrate 110 adjacent the insulating layer 170, thereby allowing current to flow between the two n-doped regions 120, 130.
As can be seen in FIG. 1, the p-doped substrate 110 forms a p-n junction with each of the n-doped regions 120, 130. Accordingly, if a negative current is applied to either of the source or drain contacts 140, 150, negative charge carriers are introduced into the respective n-doped region 120, 130. If no depletion layer is present, a parasitic diode behaviour of the p-n junction structure is activated. As a result, the negative current applied to the n-doped region 120, 130 is equivalent to applying a forward bias across the p-n junction, resulting in negative charge carriers being injected into the p-doped substrate, and thereby positive charge carriers being removed from the p-doped substrate.
FIG. 2 illustrates an example of a known protection circuit for an N-channel MOSFET 200. A source terminal of the N-channel MOSFET 200 is operably coupled to an external contact 210 of, for example, a semiconductor device (not shown) on which the N-channel MOSFET 200 is located. In this manner, the N-channel MOSFET 200 may be used to drive external devices.
As previously mentioned, if a high negative current is applied to the source or drain terminals of the N-channel MOSFET 200, parasitic diode behaviour of the p-n junction structures is activated. This parasitic diode behaviour is illustrated in FIG. 2 in the form of diodes Ds 220 and Dd 230. Also illustrated in FIG. 2 is an example of a known technique for providing protection against high negative stress current at the external contact 210.
The protection comprises a diode 240 coupled in series between the external contact 210 and ground. In this manner, when a negative current is present at the external contact 210, current is able to be drawn from ground through this diode 240, thereby significantly reducing the current drawn from the source terminal of the N-channel MOSFET 200. As a result, the injection of charge carriers into the semiconductor substrate is also significantly reduced.
However, a problem with this known technique for providing protection against high negative stress currents is that, although the diode is capable of supplying the majority of the current drawn by the negative stress current event, a not insignificant amount of current is still drawn from the N-channel MOSFET 200. As a result, some charge carriers are still injected into the semiconductor substrate. For example, in simulations comprising a negative stress current of 1 amp, the current level through the substrate reached several milliamps, which is still capable of severely disturbing the operation of components located on the substrate.
A further problem with this known technique for providing protection against high negative stress currents is that the negative voltage that may be generate at the external contact (known as a clamping voltage) is solely dependent on the specific negative stress current. This clamping voltage is not configurable, or ‘tuneable’, since it is controlled by the voltage drop caused by the diodes.
More complex techniques for providing protection against high negative stress currents are known that comprise adding specific mask technology to avoid any activation of unexpected parasitic effects. However, the cost of implementing such complex techniques is not insignificant, and as such these techniques are not an attractive solution in a competitive market.